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Cortex A8 Instruction Cycle Timing

barney vardanyan
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Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 18th March 2011 at http://forums.arm.com

    Hum !!!
    You "just need" that ;)

    I can't give you the source code of the cycle counter but I can explain how it's work.
    There Is two part:
    - the general case
    - the specific case (register restriction, shortcuts, ...)

    For the Generel case:
    It's quite easy:

    You are at cycle #10

    1 - The ARM check before starting an instruction that all the registers will be available when the instruction will need them.
    For example:
    you want to execute a MUL Rd, Rm, Rs
    Rm must be available at cycle #11 (#10 + 1 see MUL cycle table http://infocenter.ar...ch16s02s03.html)
    If at least 1 register is not avalable, then the ARM do not start the instruction and you have a stall cycle.

    2 - The ARM start to execute the instruction and lock destination registers (to prevent and other instruction using the same registers as source)
    For example with our previous MUL
    Rd is written to be lockd until cycle #16 (#10 + Rd : E5 + 1 because the mul take 2 cycle, and destination stage are always given for the last cycle of a multicyle instruction)

    3 - Free the register...
    This is quite complexe to explain but some time you can have a register locked by more than one instruction.
    For example:
    MUL r0, r1, r2
    MUL r0, r1, r2
    The first MUL will lock r0 until cycle #16. The second MUL will start at cycle #12 and lock r0 until cycle #18.
    So during cycle #13, #14 and #15 you have 2 instructions that have locked the register r0 !


    For the Specific case:
    This is less fun !!! There is a lot of case that you will have to handle.
    For exemple, You can't execute 2 instructions using the same destination register.
    I remember having post a message with this example

    mov r0, #5
    add r0, r0, r2


    MOV will lock r0 until E1.
    ADD do not need for r0 before E2.
    So there is not good reason (it must have one but I do not know it) to not execute both instructions in the same cycle.

    Finally.
    The program is not so complexe to do as it could seems.

    But !!!
    First of all, you must be sure that you understand:
    - How work the pipeline stages.
    - What is exactly a pipeline

    Well !!!
    You know now what to to for the 3 next month ;)
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  • 0 Offline
    Note: This was originally posted on 18th March 2011 at http://forums.arm.com

    Hum !!!
    You "just need" that ;)

    I can't give you the source code of the cycle counter but I can explain how it's work.
    There Is two part:
    - the general case
    - the specific case (register restriction, shortcuts, ...)

    For the Generel case:
    It's quite easy:

    You are at cycle #10

    1 - The ARM check before starting an instruction that all the registers will be available when the instruction will need them.
    For example:
    you want to execute a MUL Rd, Rm, Rs
    Rm must be available at cycle #11 (#10 + 1 see MUL cycle table http://infocenter.ar...ch16s02s03.html)
    If at least 1 register is not avalable, then the ARM do not start the instruction and you have a stall cycle.

    2 - The ARM start to execute the instruction and lock destination registers (to prevent and other instruction using the same registers as source)
    For example with our previous MUL
    Rd is written to be lockd until cycle #16 (#10 + Rd : E5 + 1 because the mul take 2 cycle, and destination stage are always given for the last cycle of a multicyle instruction)

    3 - Free the register...
    This is quite complexe to explain but some time you can have a register locked by more than one instruction.
    For example:
    MUL r0, r1, r2
    MUL r0, r1, r2
    The first MUL will lock r0 until cycle #16. The second MUL will start at cycle #12 and lock r0 until cycle #18.
    So during cycle #13, #14 and #15 you have 2 instructions that have locked the register r0 !


    For the Specific case:
    This is less fun !!! There is a lot of case that you will have to handle.
    For exemple, You can't execute 2 instructions using the same destination register.
    I remember having post a message with this example

    mov r0, #5
    add r0, r0, r2


    MOV will lock r0 until E1.
    ADD do not need for r0 before E2.
    So there is not good reason (it must have one but I do not know it) to not execute both instructions in the same cycle.

    Finally.
    The program is not so complexe to do as it could seems.

    But !!!
    First of all, you must be sure that you understand:
    - How work the pipeline stages.
    - What is exactly a pipeline

    Well !!!
    You know now what to to for the 3 next month ;)
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