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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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  • 0
    Note: This was originally posted on 13th July 2011 at http://forums.arm.com


    I am impressed by how fast you modified your code.
    I wish, I would be as good as you.
    I have just found some instructions that your module report  as unrecognized. Please check them:



    This is not so complex.
    Most of the time rules are missing or a wrong into the excel file...
    so update juste take few minutes...


    vqdmulh.s16 d0, d1, d2[0]
    vqrdmulh.s16 d0, d1, d2
    vqrdmulh.s16 d0, d1, d2[0]
    vqshlu.s32 q1, q2, #1
    vrecpe.u32 d1, d0
    vrecpe.u32 q1, q0
    vrsqrte.u32 d1, d0
    vrsqrte.u32 q1, q0
    vpmax.s16 d0, d1, d2
    vpmin.s16 d2, d1, d0
    vqdmulh.s16 d0, d1, d2


    vshll.s16 d2, q0, #1
    vshll.u16 d2, q0, #1




    Well.
    You were right for the 11 first rules.
    they were missing. I've added them

    For VSHLL
    Registers are not in the right position VSHLL take a quadword as destination register and a doubleword as source.
    So
    vshll.u16 d2, q0, #1
    is not a valid instruction.

    Thank's for the report !

    Etienne
Reply
  • 0
    Note: This was originally posted on 13th July 2011 at http://forums.arm.com


    I am impressed by how fast you modified your code.
    I wish, I would be as good as you.
    I have just found some instructions that your module report  as unrecognized. Please check them:



    This is not so complex.
    Most of the time rules are missing or a wrong into the excel file...
    so update juste take few minutes...


    vqdmulh.s16 d0, d1, d2[0]
    vqrdmulh.s16 d0, d1, d2
    vqrdmulh.s16 d0, d1, d2[0]
    vqshlu.s32 q1, q2, #1
    vrecpe.u32 d1, d0
    vrecpe.u32 q1, q0
    vrsqrte.u32 d1, d0
    vrsqrte.u32 q1, q0
    vpmax.s16 d0, d1, d2
    vpmin.s16 d2, d1, d0
    vqdmulh.s16 d0, d1, d2


    vshll.s16 d2, q0, #1
    vshll.u16 d2, q0, #1




    Well.
    You were right for the 11 first rules.
    they were missing. I've added them

    For VSHLL
    Registers are not in the right position VSHLL take a quadword as destination register and a doubleword as source.
    So
    vshll.u16 d2, q0, #1
    is not a valid instruction.

    Thank's for the report !

    Etienne
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