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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 8th August 2011 at http://forums.arm.com


    HI Etienne

    I have checked some floating-point instructions as below:
    VADD,VSUB,VABD,VMUL,VCEQ,VCGE,VCGTVCAGE,VCAGT,VMAX,VMIN

    In specs, they all require source registers at N2 stage.
    However, in your database (excel file), they require source registers at N1 stage.

    Why is this difference?


    Yes.
    There were a mistake into the excel file
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  • 0
    Note: This was originally posted on 8th August 2011 at http://forums.arm.com


    HI Etienne

    I have checked some floating-point instructions as below:
    VADD,VSUB,VABD,VMUL,VCEQ,VCGE,VCGTVCAGE,VCAGT,VMAX,VMIN

    In specs, they all require source registers at N2 stage.
    However, in your database (excel file), they require source registers at N1 stage.

    Why is this difference?


    Yes.
    There were a mistake into the excel file
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