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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 11th May 2011 at http://forums.arm.com


    How can you treat this situation (my example)?
    I guess when you know the available stage of a register is E2, you treat as below:
    - If the register is source, you know it is available at  E2
    - If the register is destination, you know it is available at  E3
    Is my guess right?


    That's quite easy in fact.
    current cycle is 1
    current pipeline is 0

    To know if you first add can be executed you must check that
    r2 must be available at cycle 1 + 2 (current cycle + stage)

    r3 must be available at cycle 1 + 2 (current cycle + stage)

    That's ok to execute.
    You mark r0 to be locked until 1 + 2 + 1 (current cycle + stage + 1 cycle)
    So r0 is locked until 4


    Now when you try to execute the second ADD
    r0 must be available at cycle 1 + 2 (current cycle + stage) = 3
    but it's lock until cycle 4... so you have to wait.
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  • 0
    Note: This was originally posted on 11th May 2011 at http://forums.arm.com


    How can you treat this situation (my example)?
    I guess when you know the available stage of a register is E2, you treat as below:
    - If the register is source, you know it is available at  E2
    - If the register is destination, you know it is available at  E3
    Is my guess right?


    That's quite easy in fact.
    current cycle is 1
    current pipeline is 0

    To know if you first add can be executed you must check that
    r2 must be available at cycle 1 + 2 (current cycle + stage)

    r3 must be available at cycle 1 + 2 (current cycle + stage)

    That's ok to execute.
    You mark r0 to be locked until 1 + 2 + 1 (current cycle + stage + 1 cycle)
    So r0 is locked until 4


    Now when you try to execute the second ADD
    r0 must be available at cycle 1 + 2 (current cycle + stage) = 3
    but it's lock until cycle 4... so you have to wait.
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