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Cortex A8 Instruction Cycle Timing

Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(

Parents

0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 17th June 2011 at http://forums.arm.com

Now I understand how hard to find cycle timing for all instructions.

Ben avison have made a very usefull work for that
http://www.avison.me.uk/ben/programming/cortex-a8.html

For not found instructions, you treat them as unrecognized, right?

Not exactly.
I added rules into the cycle counter but cycle information could be wrong.

I tried some instructions such as: SETEND, BLKP, SMI, SMC and your cycle count module said unrecognized.

I do not add this instruction because I do not know them.
And nobody used them since v0.7
If somebody put them into the cycle counter, these instruction will be put into the unrecognized instruction log file, and I'll add them.

How can I get the lastest version. Is it here: http://pulsar.websha...x-A8-cycle.xlsx
I found some instructions are updated. For example, SUBS pc, lr, #imm isn't in "cortex-A8-cycle.xlsx" but it is available in http://pulsar.websha...ult.php?lng=fr.

Yes the last rules version is always at the same place.
For SUBS !
I do not write every possible instruction. There is 2^32 possible instruction into the ARM.

I use regular expressions.
For Example: SUB is defined into sheet "Instruction" Line 26
it takes 1 cycle
it can be executed into both pipeline 0 and 1 (a&
it use ALU functional unit of the pipeline
the type of the instruction is 'data'. This information is used only with instruction that can run only one time by cycle (LDR for example)
flag: define if the instruction can be conditional and if you can use the S bit to set the flag register.
callback: the callback is used to make additional control after the regexp check... for SUB imm8plus check that the immediate value is valid.
wait: is a special field to indicated global lock operation like VMOV r0, d0
sform: is used for short mnemonic instruction (when a register can be omit).
and the all the src and dst stage...

Finally this line is transformed automatically into a regexp
/^\s*(and|eor|sub|rsb|add|adc|sbc|rcsc|orr|bic)(al|eq|ne|cs|cc|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|lo|hs)?(s)?() (\s+(r\d|r[1][012345]|sb|sl|fp|ip|sp|pc|lr)\s*, \s*(r\d|r[1][012345]|sb|sl|fp|ip|sp|pc|lr)\s*, \s*([^;@,\[\]:]*)\s*)?(?:\s(@.*|\/\/.*))?$/iU

I can't understand why there is too many cases. I guess you calculate how many registers and get how many cycle by the formula in specs.
Please explain for me if you can.

That's what I do now.
I'm using the callback to count the number of register to LOAD (or STORE) and then affect the correct number of cycle to the instruction.

About the v 0.8
The engine is now finished (i.e. I do not know what I could add again)
Now, I'll:
- add missing rules.
- improve callback quality to detect wrong instruction
- may be make a faster engine by removing functional unit handling (it seems that it is possible to do the same engine without manage functional unit).
- and test.

Etienne

I've put the right link for Ben AVISON website.
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0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 17th June 2011 at http://forums.arm.com

Now I understand how hard to find cycle timing for all instructions.

Ben avison have made a very usefull work for that
http://www.avison.me.uk/ben/programming/cortex-a8.html

For not found instructions, you treat them as unrecognized, right?

Not exactly.
I added rules into the cycle counter but cycle information could be wrong.

I tried some instructions such as: SETEND, BLKP, SMI, SMC and your cycle count module said unrecognized.

I do not add this instruction because I do not know them.
And nobody used them since v0.7
If somebody put them into the cycle counter, these instruction will be put into the unrecognized instruction log file, and I'll add them.

How can I get the lastest version. Is it here: http://pulsar.websha...x-A8-cycle.xlsx
I found some instructions are updated. For example, SUBS pc, lr, #imm isn't in "cortex-A8-cycle.xlsx" but it is available in http://pulsar.websha...ult.php?lng=fr.

Yes the last rules version is always at the same place.
For SUBS !
I do not write every possible instruction. There is 2^32 possible instruction into the ARM.

I use regular expressions.
For Example: SUB is defined into sheet "Instruction" Line 26
it takes 1 cycle
it can be executed into both pipeline 0 and 1 (a&
it use ALU functional unit of the pipeline
the type of the instruction is 'data'. This information is used only with instruction that can run only one time by cycle (LDR for example)
flag: define if the instruction can be conditional and if you can use the S bit to set the flag register.
callback: the callback is used to make additional control after the regexp check... for SUB imm8plus check that the immediate value is valid.
wait: is a special field to indicated global lock operation like VMOV r0, d0
sform: is used for short mnemonic instruction (when a register can be omit).
and the all the src and dst stage...

Finally this line is transformed automatically into a regexp
/^\s*(and|eor|sub|rsb|add|adc|sbc|rcsc|orr|bic)(al|eq|ne|cs|cc|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|lo|hs)?(s)?() (\s+(r\d|r[1][012345]|sb|sl|fp|ip|sp|pc|lr)\s*, \s*(r\d|r[1][012345]|sb|sl|fp|ip|sp|pc|lr)\s*, \s*([^;@,\[\]:]*)\s*)?(?:\s(@.*|\/\/.*))?$/iU

I can't understand why there is too many cases. I guess you calculate how many registers and get how many cycle by the formula in specs.
Please explain for me if you can.

That's what I do now.
I'm using the callback to count the number of register to LOAD (or STORE) and then affect the correct number of cycle to the instruction.

About the v 0.8
The engine is now finished (i.e. I do not know what I could add again)
Now, I'll:
- add missing rules.
- improve callback quality to detect wrong instruction
- may be make a faster engine by removing functional unit handling (it seems that it is possible to do the same engine without manage functional unit).
- and test.

Etienne

I've put the right link for Ben AVISON website.
Cancel
Vote up 0 Vote down

Cancel

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