• State Not Answered
  • Locked Locked
  • Replies 90 replies
  • Subscribers 348 subscribers
  • Views 85180 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
Parents
  • 0
    Note: This was originally posted on 14th June 2011 at http://forums.arm.com

    Hi Dung.

    for MRS and MSR: there is a lot of instruction that I've not found real cycle timing and I do not have time to test.
    In this case the rules are in the file only for parsing purpose...

    Take the last version (but keep the previous one because I've change a lot of things).
    For example I remove all the STM and LDM rules. There is to many case. Now I build this rules automaticaly in the cycle counter.

    dstCond is the cycle for destination register when the instruction is conditional. That's the case for
    MOVEQ r0, #5
    in this case r0 is written a stage 2 while without conditionnal information
    MOV r0, #5
    r0 will be written at stage 1

    In conditional instruction, destination register must be read
    cc-dst1 and cc-dst2 are the stage where destination register are read for conditional instructions.

    Etienne
Reply
  • 0
    Note: This was originally posted on 14th June 2011 at http://forums.arm.com

    Hi Dung.

    for MRS and MSR: there is a lot of instruction that I've not found real cycle timing and I do not have time to test.
    In this case the rules are in the file only for parsing purpose...

    Take the last version (but keep the previous one because I've change a lot of things).
    For example I remove all the STM and LDM rules. There is to many case. Now I build this rules automaticaly in the cycle counter.

    dstCond is the cycle for destination register when the instruction is conditional. That's the case for
    MOVEQ r0, #5
    in this case r0 is written a stage 2 while without conditionnal information
    MOV r0, #5
    r0 will be written at stage 1

    In conditional instruction, destination register must be read
    cc-dst1 and cc-dst2 are the stage where destination register are read for conditional instructions.

    Etienne
Children
No data