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Cortex A8 Instruction Cycle Timing

Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(

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0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 28th June 2011 at http://forums.arm.com

I am sorry because I am still confused. For example: ldm r1, {r2, r3}
Assuming that this instruction starts at the cycle n.
If this instruction took only 1 cycle, r2, r3 would be available at the cycle n + 3.
However, this instruction takes 2 cycle, so when are r2 and r3 available? (n + 3) or (n + 4)?

n + 4
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0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 28th June 2011 at http://forums.arm.com

I am sorry because I am still confused. For example: ldm r1, {r2, r3}
Assuming that this instruction starts at the cycle n.
If this instruction took only 1 cycle, r2, r3 would be available at the cycle n + 3.
However, this instruction takes 2 cycle, so when are r2 and r3 available? (n + 3) or (n + 4)?

n + 4
Cancel
Vote up 0 Vote down

Cancel

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