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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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  • 0
    Note: This was originally posted on 28th June 2011 at http://forums.arm.com


    I have 2 questions related to multiple load instructions. For example: ldm r1!, {r2, r3}.
    This instruction takes 2 cycle. So it is broken down to 2 single-cycle operations.
    1. Because write back is enabled, r1 is written in E2 stage. However, which single-cycle operation is r1 written? The first single-cycle operation or the second single-cycle operation?


    I've used stage 2 for pointer register of a LDM STM operation.

    2. When are r2, r3 available for other instructions? I can not find any scheduling information in specs.
    I assume this instruction is similar to LDR, that means, r2, r3 is available in E3. Because r3 is written by the second single-cycle operation, it is available in E3 of the second single-cycle operation.


    You right.
    the 2 last register are available at stage 3
    the 2 previous regsiter are available at stage 2
    the n previous register are available at stage 1.

    I'm not sure this is the real values, but this is the values I used in the cycle counter.


    If my assumption is correct, 2 below instructions should produce 2 cycle penalty:
    ldm r1, {r2, r3}
    ldr r4, [r3, #1]
    However, the result is different in http://pulsar.websha...sult.php?lng=fr
    Please explain for me.


    Use the permalink to give example !!!
    http://pulsar.websha...sample-23918fa0


    Hum. I think you're right.
    There is a problem into the cycle counter.
    I'll check...


    [Update 14.34]  : I've patch the register stage in the cycle counter. Thank's
Reply
  • 0
    Note: This was originally posted on 28th June 2011 at http://forums.arm.com


    I have 2 questions related to multiple load instructions. For example: ldm r1!, {r2, r3}.
    This instruction takes 2 cycle. So it is broken down to 2 single-cycle operations.
    1. Because write back is enabled, r1 is written in E2 stage. However, which single-cycle operation is r1 written? The first single-cycle operation or the second single-cycle operation?


    I've used stage 2 for pointer register of a LDM STM operation.

    2. When are r2, r3 available for other instructions? I can not find any scheduling information in specs.
    I assume this instruction is similar to LDR, that means, r2, r3 is available in E3. Because r3 is written by the second single-cycle operation, it is available in E3 of the second single-cycle operation.


    You right.
    the 2 last register are available at stage 3
    the 2 previous regsiter are available at stage 2
    the n previous register are available at stage 1.

    I'm not sure this is the real values, but this is the values I used in the cycle counter.


    If my assumption is correct, 2 below instructions should produce 2 cycle penalty:
    ldm r1, {r2, r3}
    ldr r4, [r3, #1]
    However, the result is different in http://pulsar.websha...sult.php?lng=fr
    Please explain for me.


    Use the permalink to give example !!!
    http://pulsar.websha...sample-23918fa0


    Hum. I think you're right.
    There is a problem into the cycle counter.
    I'll check...


    [Update 14.34]  : I've patch the register stage in the cycle counter. Thank's
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