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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 29th April 2011 at http://forums.arm.com

    for dual rules, all is here
    http://infocenter.ar...k/Babhefaj.html

    For the functional unit:
    Once the instruction have been decode, it is seended to a specific functional unit (called fu).
    Those "fu" are linked to pipelines.

    On the ARM, you have 2 pipelines and 4 fu
    ALU0
    MUL0
    ALU1
    LS (load store)

    ALU0 and MUL0 a linked to pipeline 0
    ALU1 is linked to pipeline 1

    There is no MUL1. That's why you can't execute a MUL opération into pipeline 1

    LS fu is linked to pipeline0 and pipeline1. That's why you execute only one memory access, but this acces can be done into pipeline 0 ou pipeline 1.

    On ARM you can only execute 1 MUL by cycle and 1 LDR / STR by cycle. But why these instructions can't be dual is not the same !!!

    Do you need to handle then in a cycle counter ???

    Rem : what I'll say now is not very sure ! These are only speculations (but they seems to be true) !!!
    Let suppose you have this code

    LDRD r0, r1, [r5]!
    LDR r3, [r6]!


    LDRD take 2 cycles. (and start on cycle 1 pipeline 0)
    Because it is a multicyle instruction, only the last cycle can be dual.
    LDR can be executed into pipeline 1

    So! If you just apply the ARM rules described into the link I gave you sooner. The LDR should execute into cycle 2 pipeline 1.
    For me, this is not possible because the LS unit is in use (it is in use for 2 cycles). So LDR will execute in cycle 3 pipeline 0.

    This working mode seems to be correct, but there is not many case where stall cycle are due to fu conflict !

    In fact I think the rules should be
    "Multi-cycle instructions must issue in pipeline 0 and can only dual issue in their last iteration if it does not use the same functional unit."
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  • 0
    Note: This was originally posted on 29th April 2011 at http://forums.arm.com

    for dual rules, all is here
    http://infocenter.ar...k/Babhefaj.html

    For the functional unit:
    Once the instruction have been decode, it is seended to a specific functional unit (called fu).
    Those "fu" are linked to pipelines.

    On the ARM, you have 2 pipelines and 4 fu
    ALU0
    MUL0
    ALU1
    LS (load store)

    ALU0 and MUL0 a linked to pipeline 0
    ALU1 is linked to pipeline 1

    There is no MUL1. That's why you can't execute a MUL opération into pipeline 1

    LS fu is linked to pipeline0 and pipeline1. That's why you execute only one memory access, but this acces can be done into pipeline 0 ou pipeline 1.

    On ARM you can only execute 1 MUL by cycle and 1 LDR / STR by cycle. But why these instructions can't be dual is not the same !!!

    Do you need to handle then in a cycle counter ???

    Rem : what I'll say now is not very sure ! These are only speculations (but they seems to be true) !!!
    Let suppose you have this code

    LDRD r0, r1, [r5]!
    LDR r3, [r6]!


    LDRD take 2 cycles. (and start on cycle 1 pipeline 0)
    Because it is a multicyle instruction, only the last cycle can be dual.
    LDR can be executed into pipeline 1

    So! If you just apply the ARM rules described into the link I gave you sooner. The LDR should execute into cycle 2 pipeline 1.
    For me, this is not possible because the LS unit is in use (it is in use for 2 cycles). So LDR will execute in cycle 3 pipeline 0.

    This working mode seems to be correct, but there is not many case where stall cycle are due to fu conflict !

    In fact I think the rules should be
    "Multi-cycle instructions must issue in pipeline 0 and can only dual issue in their last iteration if it does not use the same functional unit."
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