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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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  • 0
    Note: This was originally posted on 28th April 2011 at http://forums.arm.com


    Is it right that if the next instruction uses Rd as operand, it has to wait after cycle #16 to start execution? If so, I think it is wasteful because if there no dependency, the next instruction may start execution at cycle #13 or #14.

    Is my thought right?

    Dung!


    Yes that's it... :)


    For branch :
    I'm do not know anything about the first stage of the ARM pipeline.
    I don't know what you want to do.
    But, I think that there is no way to know just with a code source if a (conditional) branch will be mispredict or not.

    I assume that a B instruction is always correctly predict.
    For a conditional branch this is the lottery.

    Is you found somewhere information about how the branch is correctly predict, I'm very interested:

    I remenber having tried something like this one day


       mov r0, #1
       mov r10, #10000

    .loop:
       nop
       nop
       rsbs r0, r0, #1
       beq .else


       subs r10, r10, #1
       beq .exit
       nop
       nop
       b .loop

    .else

       subs r10, r10, #1
       beq .exit

       nop
       nop
       b .loop

    .exit:


    I thought the branches to .else will always be mispredict, but it was not the case.
    It could be very usefull to know the prediction algorithm (but I assume it must be quite secret ;) )!!!
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  • 0
    Note: This was originally posted on 28th April 2011 at http://forums.arm.com


    Is it right that if the next instruction uses Rd as operand, it has to wait after cycle #16 to start execution? If so, I think it is wasteful because if there no dependency, the next instruction may start execution at cycle #13 or #14.

    Is my thought right?

    Dung!


    Yes that's it... :)


    For branch :
    I'm do not know anything about the first stage of the ARM pipeline.
    I don't know what you want to do.
    But, I think that there is no way to know just with a code source if a (conditional) branch will be mispredict or not.

    I assume that a B instruction is always correctly predict.
    For a conditional branch this is the lottery.

    Is you found somewhere information about how the branch is correctly predict, I'm very interested:

    I remenber having tried something like this one day


       mov r0, #1
       mov r10, #10000

    .loop:
       nop
       nop
       rsbs r0, r0, #1
       beq .else


       subs r10, r10, #1
       beq .exit
       nop
       nop
       b .loop

    .else

       subs r10, r10, #1
       beq .exit

       nop
       nop
       b .loop

    .exit:


    I thought the branches to .else will always be mispredict, but it was not the case.
    It could be very usefull to know the prediction algorithm (but I assume it must be quite secret ;) )!!!
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