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Cortex A8 Instruction Cycle Timing

Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(

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0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 5th May 2011 at http://forums.arm.com

[font=arial, verdana, tahoma, sans-serif][size=2]

I read from specs that a Neon load/store instructions can be dual issued with SIMD data-processing instructions. So I tried below code in your website:
vld1.32 {d0}, [r0]
vadd d1, d2, d3

Hum.
That's exactly a case where, for the moment, I'm not agree with the documentation.
Read this post
http://pulsar.websha...bowels-of-neon/

I've made new tests !!!
For me, cycle of the documentation are "quite" correct. but you can't have a dual issue if the load/store instruction take more than 1 cycle.

I'm not sure about that yet, I currently make additional tests...

the current cycle counter version does not handle the dual issued instruction with memory acces
It's written here [/size][/font]
http://pulsar.webshaker.net/2011/04/12/program-to-count-the-cycles-of-the-a8-cortex-v0-6/
or here (for french)
http://pulsar.webshaker.net/2011/04/12/programme-pour-compter-les-cycles-du-cortex-a8-v0-6/

...but the next version does. The new version should be online in few days !
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0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 5th May 2011 at http://forums.arm.com

[font=arial, verdana, tahoma, sans-serif][size=2]

I read from specs that a Neon load/store instructions can be dual issued with SIMD data-processing instructions. So I tried below code in your website:
vld1.32 {d0}, [r0]
vadd d1, d2, d3

Hum.
That's exactly a case where, for the moment, I'm not agree with the documentation.
Read this post
http://pulsar.websha...bowels-of-neon/

I've made new tests !!!
For me, cycle of the documentation are "quite" correct. but you can't have a dual issue if the load/store instruction take more than 1 cycle.

I'm not sure about that yet, I currently make additional tests...

the current cycle counter version does not handle the dual issued instruction with memory acces
It's written here [/size][/font]
http://pulsar.webshaker.net/2011/04/12/program-to-count-the-cycles-of-the-a8-cortex-v0-6/
or here (for french)
http://pulsar.webshaker.net/2011/04/12/programme-pour-compter-les-cycles-du-cortex-a8-v0-6/

...but the next version does. The new version should be online in few days !
Cancel
Vote up 0 Vote down

Cancel

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