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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 18th March 2011 at http://forums.arm.com

    In pipelined processor there is a difference between
    - the number of cycle needed to execute an instruction (from the beginning to the end
    - the number of cycle that the pipeline is locked.

    The mul take 6 cycles to execute when the instruction entrer into the pipeline.
    but the pipeline is blocked during only 2 cycle.

    when you execute this code

    mul r0, r1, r2
    mul r3, r4, r5


    During the cycle 2, 3, 5, 6 ARM will execute both the mul


    Explain that with mul is not a good choice because the mul take 2 cycles!
    What you need to understand is that the ARM can start a new instruction most of time every cycle, but this instruction can take more than one cycle to execute.
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  • 0
    Note: This was originally posted on 18th March 2011 at http://forums.arm.com

    In pipelined processor there is a difference between
    - the number of cycle needed to execute an instruction (from the beginning to the end
    - the number of cycle that the pipeline is locked.

    The mul take 6 cycles to execute when the instruction entrer into the pipeline.
    but the pipeline is blocked during only 2 cycle.

    when you execute this code

    mul r0, r1, r2
    mul r3, r4, r5


    During the cycle 2, 3, 5, 6 ARM will execute both the mul


    Explain that with mul is not a good choice because the mul take 2 cycles!
    What you need to understand is that the ARM can start a new instruction most of time every cycle, but this instruction can take more than one cycle to execute.
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