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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 28th April 2011 at http://forums.arm.com


    2 - The ARM start to execute the instruction and lock destination registers (to prevent and other instruction using the same registers as source)
    For example with our previous MUL
    Rd is written to be lockd until cycle #16 (#10 + Rd : E5 + 1 because the mul take 2 cycle, and destination stage are always given for the last cycle of a multicyle instruction)



    Is it right that if the next instruction uses Rd as operand, it has to wait after cycle #16 to start execution? If so, I think it is wasteful because if there no dependency, the next instruction may start execution at cycle #13 or #14.

    Is my thought right?

    Dung!
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  • 0
    Note: This was originally posted on 28th April 2011 at http://forums.arm.com


    2 - The ARM start to execute the instruction and lock destination registers (to prevent and other instruction using the same registers as source)
    For example with our previous MUL
    Rd is written to be lockd until cycle #16 (#10 + Rd : E5 + 1 because the mul take 2 cycle, and destination stage are always given for the last cycle of a multicyle instruction)



    Is it right that if the next instruction uses Rd as operand, it has to wait after cycle #16 to start execution? If so, I think it is wasteful because if there no dependency, the next instruction may start execution at cycle #13 or #14.

    Is my thought right?

    Dung!
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