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aarch64 Exception Level Sw itch from EL1 to EL0

michaelyuanfeng

Hi Expert,

I am working on a simple kernel and test it on Qemu which supports RasPi3. During the boot level. Ras Pi goes to EL3 level, and I set spsr_el3 to 1 and elr_el3 to kernel_main and then use eret to enter EL1 mode. My problem is I create a kernel thread which still in EL1 level. I want to switch the kernel thread to user level. What I did is that this kernel thread also set spsr_el1 to 0 and elr_el1 to a function pointer, then eret. But this case a sync interrupt, I think caused by this eret? Please help her

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  • +1 in reply to michaelyuanfeng

    Check the ARMv8-A manuals:

    EC == 100100
    Data Abort from a lower Exception level, that might be using AArch32 or AArch64.
    Used for MMU faults generated by data accesses, alignment faults other than those
    caused by Stack Pointer misalignment, and synchronous External aborts, including
    synchronous parity or ECC errors. Not used for debug related exceptions.
    This value is valid for all described registers.

    So likely, the MMU setup is wrong.

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  • +1 in reply to michaelyuanfeng

    Check the ARMv8-A manuals:

    EC == 100100
    Data Abort from a lower Exception level, that might be using AArch32 or AArch64.
    Used for MMU faults generated by data accesses, alignment faults other than those
    caused by Stack Pointer misalignment, and synchronous External aborts, including
    synchronous parity or ECC errors. Not used for debug related exceptions.
    This value is valid for all described registers.

    So likely, the MMU setup is wrong.

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