I'm using a cortex-a53 FVP model. It comes only with GICv3, but by reading the ICC_SRE_EL3.SRE bit I see this implementation has legacy support.
Before leaving EL3 I configure all interrupts to group 1 in the distributor and set the PMR in the interfaces to the lowest priority (highest value) possible.
After entering EL2 and configuring and enabling group 1 in the distributor and interfaces I trigger an SGI (which was previously enabled and set to the highest priority). In the distributor, it all seems working fine the interrupt becomes pending, but the target interface never sees it.
Do I need to configure anything else to get the legacy to work just as GICv2? I'm am also disabling IRQ group 1 bypass.
Thank you in advance
Edit: I actually validated the code works on an actual GICv2 by running the code on a Xilinx ZCU104 board.