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I'm using a cortex-a53 FVP model. It comes only with GICv3, but by reading the ICC_SRE_EL3.SRE bit I see this implementation has legacy support.
Before leaving EL3 I configure all interrupts to group 1 in the distributor and set the PMR in the interfaces to the lowest priority (highest value) possible.
After entering EL2 and configuring and enabling group 1 in the distributor and interfaces I trigger an SGI (which was previously enabled and set to the highest priority). In the distributor, it all seems working fine the interrupt becomes pending, but the target interface never sees it.
Do I need to configure anything else to get the legacy to work just as GICv2? I'm am also disabling IRQ group 1 bypass.
Thank you in advance
Edit: I actually validated the code works on an actual GICv2 by running the code on a Xilinx ZCU104 board.
You have to "wake up" the redistributor. At least I had to on a i.MX8MQ (though legacy support seems to be broken on this chip).
Unfortunately, this was not enough. Still no response.
EDIT: My bad! This was it! However, I was not able to solve this programmatically. This is was the code I was using:
gicr.WAKER &= ~0x2; while(gicr.WAKER & 0x4);
gicr is a volatile packed struct conforming with the redistributor offsets mapped as device memory nGnRnE. Watching the WAKER register using the debugger, it had 0x6 reset value, and this code actual had the expected behaviour - both bits (2 and 3) were cleared, when only clearing bit 2. However, this affected the register observed by any of the cores, which I found odd since I had the idea each core had a private redistributor.
The way I solved it was passing -C gic_distributor.wakeup-on-reset=true to the model. This option is described in the documentation as: "# (bool , init-time) default = '0' : Go against specification and start redistributors in woken-up state at reset. This allows software that was written for previous versions of the GICv3 specification to work correctly. This should not be used for production code or when the distributor is used separately from the core fast model."