Hi all:
I have some questions about DMB and DSB in armv8.
(1)
In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".
But in ARM Cortex-A Series Programmer’s Guide for ARMv8-A doc, it explains some dmb/dsb parameters.for example :
<option> | Ordered Accesses (before – after) | Shareability Domain LD | Load –Load, Load – Store | Full system
Load - Load/Store:This means that the barrier requires all loads to complete before the barrier butdoes not require stores to complete. Both loads and stores that appear after thebarrier in program order must wait for the barrier to complete.
Since Load - Load/Store means the barrier requires all loads to complete before the barrier, I think it has ensured the completion of memory access, so I am confused.
(2)
In ARM Cortex-A Series Programmer’s Guide for ARMv8-A doc, it also says DSB "enforces the same ordering as the Data Memory Barrier, but has the additional effect of blocking execution of any further instructions, not just loads or stores, or both, until synchronization is complete".
Since DSB can block any instructions, what's "ST" in "DSB ST" for?
(3)
I have already knew that DSB can replace DMB safely, but in what situation should we only use "DSB", not "DMB"? what's the difference between DSB and DMB? An example should be great.
Thanks!
Thank your for the reply.
I am still trying to understand the difference between observation and completion of memory access, but have not got the point. It seems difficult for me to understand. Can you give me a hand?
AFAIK, "observation" means, the other PEs "see" there is something going on and a cache line is dirty.
"completion" means, the memory access has been done completely, means the data written is actually in the memory.
One more additional aspect about completion is that for transfers that are not cached not buffered (e.g. reading a peripheral register), the completion happens when the processor received the response of the transaction (e.g. OKAY/ERROR). Depends on the bus system design, the response received from the transfer could be different from the order of the data reaching the memory system.
Thank you very much!
It helps me a lot.