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Hi,
We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify the corresponding address. In Cortex R5, we are taking these information from Instruction Fault Status Register (IFSR) and Instruction Fault Address Register (IFAR).
But in Cortex M4 processor, we understand that "prefetch abort" exception can be captured using BusFault exception (BFSR.IBUSERR). But as per M4 reference manual, we understand that the processor does not update the Bus Fault Address Register (BFAR). Kindly confirm whether our understanding is OK or not. Also please provide the information to get the address corresponding to "prefetch abort".
Regards,
Dinesh
Sorry for the inconvenience caused.
I need to confirm that there is no way to get the address information during "prefetch abort". Is there any other exception which is related to "prefetch abort" other than Bus fault? I didn't see anything on TRM that is why I said, need confirmation.
the exception stack frame has the stacked PC address which is the information you needed.
When Bus Fault exception occurred, I hope the PC address will be the exception handler start address (ISR address). Please get back with your comments
Yes, PC address will be fault handler starting address obtained from the vector table. But the faulting PC value is not lost - When when entering exception handler, a number of registers are pushed to stack and one of them is the PC value when the fault take place. Exception stack frame is shown in section 2.3.7 of Cortex-M4 Devices Generic User Guide:
http://infocenter.arm.com/help/topic/com.arm.doc.dui0553b/DUI0553.pdf
A number of webpages has examples of how to extract the stack frame (e.g. https://community.arm.com/iot/embedded/f/discussions/4749/error-hard-fault-handler )
regards,
Joseph
Thank Joseph for the detailed reply.
From this, I understand that LR (Link Register) will be pushed in to stack before running the ISR and this LR will provide the actual exception handler return address. But as per "Table 2-17 Exception return behavior", I have a doubt that whether this LR will give the exact address of the instruction which causes the exception. Kindly get back with your comments.
No, not the LR. Please look at Figure 2-3 Exception stack frame in http://infocenter.arm.com/help/topic/com.arm.doc.dui0553b/DUI0553.pdf
The 7th word in the stack frame is the stacked PC value and that is the value you wanted.
Thanks Joseph for pointing out the misunderstanding and to provide the specific answer. We will check this stacked PC value to identify the address of the instruction which causes the exception