Architectures and Processors forum Cortex-M unintentional Flash Read-While-Write

Options

How was your experience today?

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-M unintentional Flash Read-While-Write

piotr_r over 6 years ago

Hello, I am developing a bootloader for the ARM Cortex M7. All the functions that modify (either write or erase) the internal Flash are run from the RAM memory, the other code is run from the internal Flash. So there are RAM <-> Flash transitions in the bootloader execution flow. It works just fine. But there is one thing that I would like to consult with the experts. I'd like to ask if either cache or the processor's processing pipeline, with e.g. speculative fetches and branch prediction, can be a safety concern in that case. I'd like to know answers to the following questions: 1) If the code is being executed from RAM, but the MCU decides to fetch code from the internal Flash, when the Flash is being written at the same time. Is it Flash access that may cause the processor to stall or do something unexpected? 2) If yes, then how to prevent it? I will appreciate your help. Thanks, Piotr