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Behavior for other data on a STR (ARMv7-A)

When the following line is executed, what is the behavior with respect to the other words in the cache line?

STR r1, [r0]

The 4 bytes of data in r1 is written to the address in r0. But cache-lines are 32 bytes long. Assuming write-through (and ignoring store-buffers), are all 32 bytes written to backing memory?

I think that this is how the cache behaves, and this question seems to confirm it: https://community.arm.com/processors/f/discussions/1318/memory-acces-and-cache/4282#4282

I haven't found anything explicit in the ARM ARM about this, so a pointer to the right page there would also really be appreciated!

Thanks,

James

Top replies

42Bastian Schick over 7 years ago +2 verified

I think CWG in CTR (B4.1.42 CTR, Cache Type Register, VMSA) is a good hint. CWG, bits[27:24] Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction...