MIPS of Arm cortex m7

Hi Jovan,

In your paper you mentioned about the performance measurement based on toggling of I/O pin by software. Please note in MCU designs the I/O toggling rate can be limited by many factors:

- In many MCU designs GPIO peripherals are connected in a peripheral bus which can be running at different clock frequency than the processor. The bus bridge between the processor's system bus and the peripheral bus might introduce delay.

- The peripheral's programming model can have direct impact to toggling speed (i.e. can be pin be toggled with a single write operation? or does it need to performance a read-modify-write which take longer?)

- The maximum toggling rate of the I/O pin can be a limitation (i.e. some I/O pads might need to support high drive current and this requirement affect transistor switching speed).

- The choice of bus protocol of the peripheral can affect the maximum toggling speed. If using AMBA APB protocol, you need at least two clock cycles per transfer. Using AHB can reduce that to 1, depends on processor's implementation - single data access on Cortex-M0/M0+ take two clock cycles to accommodate the pipeline nature of AHB with minimum gate count. But Cortex-M0+ also has an optional single cycle I/O interface that can be used for high speed I/O peripherals. So a 72MHz Cortex-M0+ microcontroller could toggle a GPIO pin at 72MHz.

- Superscalar processor feature cannot be applied to typical peripheral I/O accesses. If there are two successive writes to a GPIO register, they will be serialized as the peripheral bus interface can only deal with one transfer at a time.

So in general, GPIO toggling speed is not correlated to processor's data processing performance.

Regarding general data processing performance, Dhrystone and CoreMark are very popular.

I noticed you used Linapck DP (double precision), but STM32F7 series you used only implemented single precision floating point unit. If you use STM32H7 (which I believe was released after your paper published), then it has DP FPU. Alternatively, Microchip (was Atmel) Cortex-M7 devices (300MHz) and NXP iMX RT (600MHz) do have double precision support in the FPU. That might give you a higher benchmark results.

regards,

Joseph

Hi Jovan,

In your paper you mentioned about the performance measurement based on toggling of I/O pin by software. Please note in MCU designs the I/O toggling rate can be limited by many factors:

- In many MCU designs GPIO peripherals are connected in a peripheral bus which can be running at different clock frequency than the processor. The bus bridge between the processor's system bus and the peripheral bus might introduce delay.

- The peripheral's programming model can have direct impact to toggling speed (i.e. can be pin be toggled with a single write operation? or does it need to performance a read-modify-write which take longer?)

- The maximum toggling rate of the I/O pin can be a limitation (i.e. some I/O pads might need to support high drive current and this requirement affect transistor switching speed).

- The choice of bus protocol of the peripheral can affect the maximum toggling speed. If using AMBA APB protocol, you need at least two clock cycles per transfer. Using AHB can reduce that to 1, depends on processor's implementation - single data access on Cortex-M0/M0+ take two clock cycles to accommodate the pipeline nature of AHB with minimum gate count. But Cortex-M0+ also has an optional single cycle I/O interface that can be used for high speed I/O peripherals. So a 72MHz Cortex-M0+ microcontroller could toggle a GPIO pin at 72MHz.

- Superscalar processor feature cannot be applied to typical peripheral I/O accesses. If there are two successive writes to a GPIO register, they will be serialized as the peripheral bus interface can only deal with one transfer at a time.

So in general, GPIO toggling speed is not correlated to processor's data processing performance.

Regarding general data processing performance, Dhrystone and CoreMark are very popular.

I noticed you used Linapck DP (double precision), but STM32F7 series you used only implemented single precision floating point unit. If you use STM32H7 (which I believe was released after your paper published), then it has DP FPU. Alternatively, Microchip (was Atmel) Cortex-M7 devices (300MHz) and NXP iMX RT (600MHz) do have double precision support in the FPU. That might give you a higher benchmark results.

regards,

Joseph

Hi Joseph,

Thank you for thorough remarks, regarding GPIO pins I/O toggling speed,  as I say my in paper my intention was not to use port registers or low level languge bit manipulation. My interest was to give insight on how fast are functions in high level programing languges that manipulate with GPIO ports.

Regarding M7 DP FPU I tested STM32F767 ARM Cortex M7 that have duble precision, as well as STMF746 with Single Precision FPU so you can se clear contrast in performance increase.

Best regards,

Thanks Jovan. Ah, I didn't realize STM32F767 implemented the double precision FPU. I thought it was available only on STM32H7 series. Sorry for the noise :-)