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Hi,
Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when processing the interrupt. I understand the use of the barrier when accessing main RAM, but does it make sense for registers?
CPU: A53 aarch64
Thanks
Hi there,
If the two accesses are to the same device, architecturally the access order is guranteed. So when handling peripheral programming sequence, there is no need to insert memory barrier between each access.
The situation is a bit more complex if the two accesses are to two different bus slaves. As seem in table A3-8 of Armv7-M architecture reference manual (link), if two accesses are both device type, but different attribute (one shareable and one non-shareable), it is allowed to have the two accesses being out of order. In the example code from the page you mentioned, it is unclear that whether the two registers are from the same slave. Also, in the context of peripheral reset, the software developer might need to take into account of peripheral/device specific behavior : if the reset does take multiple clock cycles, use of the memory barrier by itself might not be enough.
regards,
Joseph
Thank you again Joseph Yiu for the clarification. wish the article was more detailed.