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Hi,
Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when processing the interrupt. I understand the use of the barrier when accessing main RAM, but does it make sense for registers?
CPU: A53 aarch64
Thanks
Joseph, but, if the memory mapped device is strongly ordered memory, then an memory barrier gives no benefit, right? Even speculative reads should not happen in strongly ordered memory. At least, that's what I thought.
Hi Bastian,
Strongly ordered (SO) memory accesses have ordering requirements against accesses to other SO or Device address locations, but not against other "Normal" memory accesses. See table 2 in the following link:
infocenter.arm.com/.../BIHJIIIC.html
This document is for Cortex-M but the same memory ordering concept present in Cortex-A and Cortex-R.
regards,
Joseph
Update: I forgot to mention that in Armv7-M, there was a change in the memory ordering requirement.
In revision C of the Armv7-M Architecture Reference Manual, SO accesses do have ordering restrictions with Normal memory accesses.
In revision D of the Armv7-M Architecture Reference Manual, this is changed to align with other Arm processor designs.
Thanks Joseph, I missed the "strongly" vs. "normal" point.