Hi,
I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling with,
1) High priority interrupt ISR is executing and does a PendSV (assume PendSV is lower logical priority than the high priority interrupt) in its execution path, then immediately raises the priority of PendSV in the NVIC to something logically higher than the currently running interrupt. Will PendSV fire immediately because it is higher priority and pending?
2) PendSV ISR is executing, and a higher priority interrupt fires. The processor moves to the ISR of the higher priority interrupt, and the active PendSV interrupt is moved to the pending state. The higher priority interrupt raises the priority of the PendSV interrupt to something higher than itself. Will PendSV fire immediately because it is higher priority and pending?
Thanks for any insight!