Interruptible Instructions on Cortex-M4

The ARM Cortex-M4 Processor Technical Reference Manual states:

To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction from the beginning. The processor implements the Interruptible-continuable Instruction field. Load multiple (LDM) operations and store multiple (STM) operations are interruptible. The EPSR holds the information required to continue the load or store multiple from the point where the interrupt occurred.

The Definitive Guide to Cortex-M3 and Cortex-M4 Processors Third Edition states:

Some of the instructions take multiple clock cycles to execute. If an interrupt request arrives when the processor is executing a multiple cycle instruction, such as an integer divide, the instruction could be abandoned and restarted after the interrupt handler completes. This behavior also applies to load double-word (LDRD) and store double-word (STRD) instructions.
In addition, the Cortex Ò -M3 and Cortex-M4 processors allow exceptions to be taken in the middle of Multiple Load and Store instructions (LDM/STM) and stack push/pop instructions. If one of these LDM/STM/PUSH/POP instructions is executing when the interrupt request arrives, the current memory accesses will be completed, and the next register number will be saved in the stacked xPSR (Interrupt-Continuable Instruction [ICI] bits). After the exception handler completes, the multiple load/store/push/pop will resume from the point at which the transfer stopped.

So both agree, that LDM/STM/PUSH/POP instructions can be interrupted and are continued where they stopped, when the interrupt is handled.

However, the Technical Reference Manual only mentions the divide instruction as another interruptible instruction. The Definitive Guide is much more vague on this, allowing it for all multi-cycle instructions (Which are all instructions taking more than 1 cycle to execute?), mentioning divide and LDRD/STRD as examples.

So what is actually the case for a Cortex-M4 processor? Are only the divide instructions abortible and will be restarted after an interrupt, as the TRM states? Is this an implementation specific detail and I have to assume that any multi-cycle instruction may be aborted and restarted, depending on the vendor?

If it helps, the background for my question is micro-architecture--aware analysis and having a clear statement on which instructions are executed atomically would help greatly to model interrupt impact.

Thank you in advance for your help.

Kind regards