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Hi, I am new to ARM architecture and as of now exploring GIC Controller GIC-400 and using ARM Cortex a57.
Sorry for asking very fundamental flow of interrupts handling GIC-Virtual extension
Let assume a physical interrupts acknowledged by hypervisor in EL2 , then it injects the virtual interrupt to VM by writting List registers in virtual CPU interface.
Then hypervisor writes GICC_EOIR register for priority drop (my question : what does priority drop means ? does interrupt controllers stops firing further interrupts ?)
Hypervisor returns from isr, than VM triggered with IRQ handler (my question : does processor has seperate vIRQ line inside ? how does GIC takes processor to EL1 IRQ handler when List registers are updated ? )
and VM has to acknowledge interrupt by reading GICV_IAR to change state of interrupt in GICV_IAR register.
what are the next flow ? should VM end the interrupt (GICV_EOIR) and also deactivate (GICV_DIR) ? should also hypervisor implement GICC_DIR to deactivate interrupt ?
You could take a look at the "GICv3 Software Overview":http://infocenter.arm.com/help/topic/com.arm.doc.dai0492b/GICv3_Software_Overview_Official_Release_B.pdfChapter 8 covers virtualization and the list registers. While you're using GICv2, the same basic principles apply in GICv3. So the general explanation still holds.