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Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.
The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two cycles required to read full 32-bit DWORD.
What actually happens to the D16..D31 data lines on the cpu during such 16-bit read cycles?
Are they left in high-impedance mode? Are they driven?
I would like to make my custom board with two variants: one with a single 16-bit flash memory and other with dual flash memory (two 16-bit chips in parallel).
Both flash chips share address bus, CE, OE, WE signals, they just handle lower or upper 16-bits of the 32-bit data bus, respectively.
If the CPU is handling 16-bit read transactions, the other flash chip connected to the upper half data bus will see the CE and OE and will try to drive the D16..D31.
And I wonder about the compatibility of the CPU configured for 16-bit mode on a board with both flash chips populated.
Will the CPU play nicely keeping D16..D31 in high impedance mode during 16-bit cycles or will it drive these pins somehow causing collisions?
I observe bus conflict on my PCB using LPC4088 cpu by NXP.
Processor is for some reason driving L on D16-D31 during 16-bit read cycles to Flash memory.
Very unexpected: I see about 1V on D31 instead of full 3.3V driven by blank flash memory.
I have no pull-up resistors on the data lines.
I'm afraid you need to ask NXP support, or post the question on NXP community (https://community.nxp.com/community/lpc) to see if they can provide you with an answer. (The memory interface part is not a part of the Cortex-M4). Please also double check the configuration code for the memory interface to see if there is any programmable options to force the upper 16-bit to tristate.
regards,
Joseph