This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-A53 Cache protection

Hello all,

The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC-DED) and for L1 D-cache dirty (which is SED-SEC) triggered due to a load, store or preload instruction, or due to the hardware prefetcher.

My questions is: what type of abort is generated in these two cases, synchronous data aborts or asynchronous SystemErrors? Or is just the pin nINTERRIRQ set?

Thank you in advance!