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Cortex M7 D cache activated without MPU been enabled

Wess

Hi,

I have question related to cortex M7 cache behavior.

I noticed that whenever the MPU is disabled after power on reset then I activate data cache I get a hardfault (data cache is already invalidated before enabling data cache).

This doesn't make sense for me because there is default attribute for memory map and the code is executing from address above 0x20000000 which is market following ARM specification as normal cacheable.

So is there any conflit may happen when running such scenario?

Many thanks in advance.

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