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the means of tail-chaining of interrupts

xiasxian

hellow

     I am reading the book  “Cortex  -M3 Embedded Software Development” on page of 3,chapter 1.1 Nested Vectored Interrupt Controller (NVIC),

i don not understand  the means of tail-chaining of interrupts .In the sentence of  "The NVIC also supports tail-chaining of interrupts." so i finding the answer in

here. 

 thanks

Parents
  • 0 Arm Employee Badge

    Hi

    Tail-chaining is back-to-back processing of exceptions without the overhead of state saving and restoration between interrupts. The processor skips the pop of eight registers and push of eight registers when exiting one ISR and entering another because this has no effect on the stack contents.

    The processor tail-chains if a pending interrupt has higher priority than all stacked exceptions.

    I hope this helps.

    Stuart

Reply
  • 0 Arm Employee Badge

    Hi

    Tail-chaining is back-to-back processing of exceptions without the overhead of state saving and restoration between interrupts. The processor skips the pop of eight registers and push of eight registers when exiting one ISR and entering another because this has no effect on the stack contents.

    The processor tail-chains if a pending interrupt has higher priority than all stacked exceptions.

    I hope this helps.

    Stuart

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