We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.
While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness a IMPLEMENTATION DEFINED fault (Unsupported Exclusive or Atomic access) fault. This has been triggered by the following code:
typedef atomic_flag lock_t; void lock_lock(lock_t *lock) { while (atomic_flag_test_and_set_explicit(lock, memory_order_acquire)) { wfe(); } }
It is compiled to the ldaxrb/stxrb instruction, which seem to trigger this fault on this CPU.
1) Can anyone explain to me why we need caches to be activated to use exclusive access instructions ?
2) Is it possible to get a "uncached" configuration which still support exclusive access, to help us debug our DMA situation ?
Best,
V.
Hi Vincent Siles,
The ARMv8-A Reference Manual has a chapter corresponding to what you describe I think:
"Exclusive access instructions and Shareable memory locations"
It lists the memory types for which it is architecturally guaranteed that a global Exclusives monitor is implemented.
I don't think device nGnRnE is in that list, which means an implementation is allowed to have a number of listed behaviours.
One of the allowed behaviour is indeed to generates an IMPLEMENTATION DEFINED MMU fault.
Best regards,
Vincent.
Thank you for the feedback, I'll check this chapter right away