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excuse me for my English!!!
i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.
i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code for LS1043A.Any changes i have to do for that xilinx code.
Is all V8,A53 core processors have same cache, vector table address and vector handlers.
i'm new to arm coding. please help me. Any small help will be greatfull.
Thank you.
vector table => Core, all Armv8-A are the same (not sure about the Aarch32 only ones, though)cache => SoC dependent, but mostly the cache flush/invalidate routines read the respective registers.So the basic code from Xilinx should work on any other C53. But all SoC specific (like DDR setup), needs to be rewritten.
Thank you 42Bastian Schick.can you tell me one thing, that is setting up the MMU is same or not. And if i change the DDR START and END addresses will it work?if not can you suggest me other alternatives?
MMU setup depends on the SoC. DDR start and end is on thing. But also internal RAM (sometimes called OCM OnChipMemory) and peripherals.
Mr. Bastian, is .bss section is depended on the core?can i directly use that?
Hmm I think you should read about ELF format. You are mixing file format and structure with CPU internals
.bss is the uninitialized data segment of an ELF file.