Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Open Source Software and Platforms
Open Source Software and Platforms
Wiki CMSIS-RTOS2 Blinky Low Power Example
  • Help
  • Jump...
  • Cancel
  • About this wiki
  • Supported platforms
  • Obtaining support
  • +Arm Reference Platforms deliverables
  • +A-class platforms
  • -M-class platforms
    • -IoT Subsystems
      • Corstone-300 Platforms
      • +Beetle development board
      • -Musca development boards
        • Musca Platforms Links & Resources
        • +Musca-A development board
        • +Musca-B1 development board
        • -Musca-S1 development board
          • Musca-S1 Frequently Asked Questions
          • Musca-S1 Links & Resources
          • Musca-S1 Firmware update & QSPI/MRAM boot recovery
          • Board automatic run on power up
          • Keil Support for Musca-S1
          • -Musca-S1 Software Examples
            • Bare-Metal Low Power Example
            • CMSIS-RTOS2 Blinky Example
            • CMSIS-RTOS2 Blinky Low Power Example
        • Configuring S/NS Memory in an Armv8-M System
  • +R-class platforms
  • +FPGA prototyping boards
  • +Open source software

You are currently reviewing an older revision of this page.

  • History View current version

CMSIS-RTOS2 Blinky Low power Example

The 'Blinky' project is a simple CMSIS-RTOS2 Keil RTX5 based example for ARM 'Musca-S1 CM33 #0' device using ARM 'V2M-Musca-S1' Evaluation Board. Compliant to Cortex Microcontroller Software Interface Standard (CMSIS).

Example functionality:

  • Clock Settings:
    • XTAL    =          50.00 MHZ
    • SYSCLK  =          50.00 MHz
  • one LED is flashing  with a fixed speed.

The Blinky program is available in different targets:

  • Debug:
    • Compiler optimization Level 1
    • Keil RTX5 variant 'Source'
Debug (eMRAM)
code: eMRAM
data: eMRAM
idle: eMRAM off
        SRAM off
        + sleepdeep

Configure the board's BOOT switch to "MRAM".

How it works:

  •   SRAM3 is used as 'ULP RAM' which means that it is active during power down phase.
  •   Code and Data for ulp_* files are placed in ULP RAM because code is used to enter and leave power down phase.
  •   Interrupt vecors are copied to ULP RAM because S32K Timer interrupt is used for wake up.
  •   Main stack is placed in ULP RAM.
  •   Process stack is placed in ULP RAM during pwer down phase.
  •   OS Idle Thread checks if system can enter power down phase.