As we move to an autonomous world of self-driving cars and other intelligent systems, there are two undeniable truths that present new challenges to the designers: Complexity and safety.
These systems require significant processing power, resulting in many CPUs integrated into a single device, and software workloads shared across multiple processors with hypervisor or similar technology. These systems are safety-critical, with increased scrutiny applied to debug, testing, validation, and code coverage analysis. With a limited number of pins available on the SoC, the designer must make system trade-off decisions between dedicated debug interfaces and other functionality.
To help address these design trade off decisions, Arm developed the CoreSight SoC-600 library of debug IP. Traditionally a (JTAG-based) debug port is provided, alongside a trace port, using either many pins, or expensive high-speed serial interfaces. With CoreSight SoC-600, you can reuse existing interfaces on your devices, resulting in fewer resources reserved for debug use.
The (open-source) CoreSight Wire Protocol library enables you to perform on-target debug and trace through standard interfaces such as USB and TCP/IP. The Arm Debugger (part of Arm Development Studio) can use these interfaces to connect to such targets.
DSTREAM-XT enables debug and trace support for suitably designed platforms over on-target PCIe interfaces. The CoreSight SoC-600 IP is available to license from Arm, and is included as part of Arm Flexible Access.
If you can connect to the target over PCIe, why is there a need for a probe?
During any debugging phase, the target is likely to be reset frequently. This would require reinitialization of the PCIe link and enumeration of devices. This is generally not possible on the host machine without rebooting. The probe also provides isolation between target and host from any spurious memory writes on the PCIe interface that may occur during a debug session.
It is also unlikely that standard host storage would be able to keep up with the high-bandwidth trace generated. The dedicated 16GB of DDR4 memory on the probe removes this bottleneck. This data is subsequently sent to the host with a standard USB 3.0 or Gigabit TCP/IP connection.
Configurability is another big reason for a probe. A host would typically only function as a Root Complex (a collection of PCIe Root Ports) and so would only be able to connect to targets that are configured as a PCIe Endpoint. With the probe, we support both PCIe Root Port (RP) and PCIe Endpoint (EP).
The following figure shows an example configuration of how the DSTREAM-XT probe could connect to a target, with trace sources routing to the PCIe interface.
It is possible to remove the dedicated debug interface altogether, by implementing an appropriate driver on the target side to configure the PCIe interface for all debug activities.
DSTREAM-XT is Arm’s most capable debug adapter. It can support debug connections to up to 4096 CoreSight components. The probe supports PCIe 3.0 (1-8 lanes) or PCIe 4.0 (1-4 lanes), providing a total trace bandwidth of (up to) 64Gbps. This bandwidth enables many trace sources to be utilized in parallel. The probe has a 16GB on-board buffer, allowing for a deep history of trace to be recorded. Included with the probe are a variety of standard PCIe connectors to suit your target hardware. See the Arm Developer website for full specifications.
DSTREAM-XT is available to order now, with first shipments expected in July 2021, and is used with Arm Development Studio 2021.1 and later. If you are new to Arm Development Studio, a fully-featured 30-day evaluation license is available. For more information on DSTREAM-XT and all the Arm debug adapters, go to the Arm Developer website.
[CTAToken URL = "https://developer.arm.com/tools-and-software/embedded/debug-probes/dstream-family" target="_blank" text="Compare DSTREAM debug probes" class ="green"]