As I covered in the first part of this blog series, there are a number of challenges that we face when designing a Power Delivery Network (PDN) which delivers smooth supply conditions to avoid the negatives of droops and overshoots in a system. Now, we’ll look at the different components of the PDN and aim to understand their specific roles.

The power delivery network isn’t just limited to the chip – external components, namely the package and the printed circuit board (PCB), play crucial roles too. Figure 1 shows a very simplistic representation of the PDN, consisting of the chip, the package and the PCB.

Figure 1. The System Level Power Delivery Network - It consists of the chip, the package and the PCB each with its own parasitic components. These parasitics are the root-cause of non-idealities in the network.

The chip can be broadly modelled as a current source in series with a capacitor. The current source represents switching transistors and the capacitor represents the unswitching transistors and other explicit decoupling capacitors instantiated on-chip. These act as local, high bandwidth charge reservoirs that serve abrupt changes in the current demand, thereby filtering out noise on the supply rails. From a power delivery perspective, more decoupling capacitors (decaps) on-chip is always preferable.

However, they are not a free resource and can have an impact on leakage power and chip yield. Therefore, they can only supply a limited amount of charge before they get depleted and the current demand must be met from larger capacitors downstream in the network (off-chip, and instantiated on the package or the PCB).

These off-chip capacitors have orders of magnitude higher charge storage capabilities. On the other hand, they are limited by their parasitic resistance and parasitic inductance. In the equivalent circuit model (Figure 1), these discrete capacitors are represented by their effective series resistance (ESR) and their effective series inductance (ESL). Typically, package decaps have lower charge storage capacity, but lower parasitics, when compared to the PCB decaps.

From high school physics, you might recall that a capacitor is effectively a short at high frequencies. Another way of stating this is that at high frequencies, currents can be easily sourced from a capacitor. However, the ESL component of these discrete decaps limits their high frequency performance. In fact, at frequencies greater than their ‘self-resonance frequency’, where the current sourcing due to the capacitor is exactly counterbalanced by the current impeding capability of the ESL, the decap performance is almost entirely dominated by the ESL. In other words, the off-chip decaps behave effectively as inductors at high frequencies! The power line traces on the PCB and the package also add additional inductive parasitics that limit the efficacy of the discrete decaps at high frequency.

As can be seen in Figure 1, the equivalent circuit model of the PDN has multiple LC tank circuits. For instance, the die capacitor (C_{DIE}) forms a LC tank with the ESL of the package decaps. Looking at the PDN from the die side, the frequency domain response has multiple impedance peaks at frequencies which correspond to the resonance of the LC tank circuits. This is shown in Figure 2.

The highest impedance peak is due to the resonance between C_{DIE }and L_{PKG.} This is typically referred to as the **‘first-order resonance frequency’** and is typically in the range between 50MHz-150MHz.

*Figure 2. Frequency-domain response of the PDN showing impedance peaks at resonance frequencies*

The second- and third-order resonance frequencies are at lower frequencies, and typically in the range between 1MHz and 10MHz (second-order resonance) and around 10KHz (third-order resonance), respectively.

The highest impedance peak at the first-order resonance frequency is also manifested in the time domain response of the PDN as well. When the PDN is excited by a sudden increase in the current, also referred to as a ‘step excitation’, it sets off distinct oscillations in the PDN. The step excitation could be due to an abrupt change in the switching activity of a CPU, such as due to a branch misprediction. As shown in Figure 3, oscillations of the highest magnitude are observed at the first-order resonance frequency. There are slower frequencies corresponding to the second- and third-order resonance frequencies.

*Figure 3. Time-domain response of the PDN showing the distinct resonance frequencies*

The first-order resonance frequency stresses system guardbands the most. Therefore, in Arm Research, we have invested a great deal of effort in the direct and indirect observation of power-rail noise. I’ll discuss our efforts in this area further in the final part of this blog series.