Power Delivery for High-Performance Mobile Systems (1/3)

In the first post in a three-part blog series, Shidhartha Das explores the challenges of power delivery in designing mobile systems.

High-Performance Mobile Systems

Power delivery is a well-known challenge for high-end enterprise server and desktop-class systems. Guaranteeing a +-10% tolerance on the supply rails even while delivering a high current (>100A) at low supply voltages (~1V) is no mean engineering feat!

In contrast, mobile CPUs do not have similar constraints on power delivery, since they consume an order-of-magnitude lower current that somewhat alleviates power delivery challenges. However, in recent years, there has been an increasing trend towards high-performance CPU cores in mobile platforms enabled through a combination of vectorized execution, wider issue queues and high operating frequencies (>2GHz). On one hand, this has enabled mobile CPUs to deliver comparable performance levels that desktop computers were capable of, not so long ago. However, just as it is with enterprise server systems, high peak power consumption is often the price that has to be paid for high performance, even in the mobile world.

Peak Power Consumption

You may have noticed my use of the phrase ‘peak power consumption’ rather than just ‘power consumption’. This distinction is an important one during power system design and isn’t just a play on words. Power consumed by a CPU for typical computational workloads may be hugely different from that consumed for some niche workloads, that demand very high performance at the expense of very high power. These niche workloads – for instance, a gaming workload that could require solving complex physics calculations, or a machine learning workload that could require heavyweight DSP computations – stress the system by maximally exercising its compute capability. In doing so, they cause maximum switching activity that in turn manifests as peak-power consumption.

Good engineering practice dictates that we design solidly provisioned power delivery systems that can cater to the worst-case demand conditions. That means that the Printed Circuit Board must be adequately provisioned with decoupling capacitors (decaps) and the Power Management IC (PMIC) must have adequate current sourcing capabilities. I discuss the role that decaps play in filtering the power supply to on-chip transistors in part two of this blog series, but back to the story for now. All of this capability adds to the overall platform cost which may be an unacceptable overhead to pay for mobile systems that are typically sensitive to cost and form factor constraints.

Power Delivery Networks

Peak power consumption also limits a system by increasing its susceptibility to voltage noise. An ideal Power Delivery Network (PDN) provides a steady DC voltage to all the transistors on the chip. The actual supply voltage seen by transistors suffers from ‘droops’ when the supply voltage drops, or from ‘overshoots’ when the voltage rises above its ideal (or intended) levels. Under voltage-droop conditions, transistors become slower and computation therefore takes longer to complete. Voltage overshoots are also undesirable since excessive voltage bias stresses the very thin gate oxides of transistors, causing them to age at a faster rate and leading to early failures. Therefore, ideally, we would like the PDN to create smooth supply conditions that are free from droops and overshoots.

However, the reality is different (as it always is!). To understand why this is so, it is important to understand the components of the PDN and the specific roles that they play. I’ll be covering this in the next part of this blog series.

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