I am running my Linux workload on N1 SDP. According to N1 SDP documentation the SoC includes L1, L2 and L3 cache.
When I run lstopo command, I got information about 8MB L4 cache.
However when I read CLIDR_EL1 control register, I get 0xc3000123 which indicates that the “L3 cache is the highest Inner Cacheable level.”
Is The L4 cache part of CMN-600? Do I need to do something to enable it? Or it is enabled by default?
Please could you take a look at the forum directory (https://community.arm.com/developer/f) and let me know which forum I can move your question to?
Oli from the Community team
Hi again Pawel
I have moved your thread to the SoC forum.
View all questions in SoC Design forum