L4 cache in N1 SDP SoC

Hi All,

I am running my Linux workload on N1 SDP. According to N1 SDP documentation the SoC includes L1, L2 and L3 cache. 

When I run lstopo command, I got information about 8MB L4 cache. 

However when I read CLIDR_EL1 control register, I get  0xc3000123 which indicates that the “L3 cache is the highest Inner Cacheable level.”

Is The L4 cache part of CMN-600?  Do I need to do something to enable it? Or it is enabled by default?



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