Axi master initiating the incr transfer of length let's say 15 means there is total 15 write transfer are there of 4 byte on 32 bit data bus.
So now does AXI slave update the memory just after getting each transfer or only after getting 15 transfer?
That's up to the slave design, the AXI protocol only describes how the transfers are passed on the bus. If it is more efficient for the slave, and it can buffer up a number of transfers, it can update memory in bursts of received transfers.
However if the transfers are marked as non-bufferable, the slave can only return the BRESP response once those 15 write transfers have been written out to the memory (so that the master then knows the writes have completed to the final destination). Bufferable transfers can have the BRESP returned before the 15 transfers reach the memory (but only after the 15 AXI transfers have completed).
consider a single master and single slave axi communication. I am trying to understand that:
1) axi slave will update its memory with each transfer
2) it will first buffer all the 15 transfer and then update its memory.
As I said in my last message, the protocol does not define when the slave updates the memory, all the protocol defines is how the data is passed to the slave.
Both the options you describe are possible, so use whichever one works best for your application. Buffering the 15 transfers before writing to the memory might give you better performance if the memory is burst aware, but at a cost of additional buffering gates in the slave interface design.
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