If the slave asserts wait state (HREADY=0), and master asserts HTRANS =BUSY, then should the slave wait for change of HTRANS from BUSY to NONSEQ/SEQ or should the slave change the HREADY=1. This condition happens at 'Incrementing burst of undefined length'. This is a deadlock condition; something which is not clear from AHB spec.
This isn't a deadlock. The slave's data phase HREADY=0 response is for the previous address phase transfer (which must have been a NONSEQ or SEQ transfer), and is not in any way related to the current address phase transfer with HTRANS=BUSY.
So the slave should drive HREADY however it wants, adding as many wait states as it wants to the data phase of this NONSEQ/SEQ transfer.
If the master is still signaling HTRANS=BUSY when the current data phase transfer does finally compete (HREADY=1), only then does the HTRANS=BUSY transfer get sampled, and then the requirement that the slave provides a single cycle HREADY=1, HRESP=OKAY response is relevant.
So definitely no deadlock or contradictory requirements.
Got it. Thanks a lot Colin.
Hi Chanpreet Singh
Just for your information I have moved your thread to the SoC forum where it should live.
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