In APB, There are two phases. SETUP and ACCESS. The ACCESS phase is indicated by assertion of PENABLE signal. My question is why we require this phases ??
The signal PENABLE can be driven high at the same time when data and control signals are driven by master and the slave can assert the PREADY when it detects PSEL and PENABLE.
Why there is delay between assertion of PENABLE and Data/Control signals ?? Is there any reason for this delay ??
The APB protocol was designed to be simple, so no complex pipelining or timing.
So 2 phases allowed the APB master to say what it wanted (the setup phase) and then for the required transfer to occur (the access phase).
Trying to do everything in one cycle wouldn't work in synchronous logic because the peripheral being accessed won't know there is a transfer request until the end of the first cycle, which for a read access means you will always need a second cycle. Or even for write acesses, the peripheral needing to signal wait states won't know to drive PREADY low until it has sampled PSEL/PADDR/PWRITE etc, so again requiring a second cycle for this peripheral decision to be synchronously made and sampled.
If you want higher performance, lower latency accesses, use a more complex "system" bus, such as AHB or AXI, and accept more complex interface designs.
I'm not sure what the delay from PENABLE to the Data/Control signals is that you refer to. Control signals (PSEL, PADDR, PWRITE, PPROT etc) are driven at the start of the "setup" phase, and PENABLE is driven once cycle later at the start of the "access" phase. It is only PREADY, PSLVERR and PRDATA that are changed during the "access" phase, and there you do PENABLE going high at a time when those PREADY/PSLVERR and PRDATA signals can be changing. But PENABLE, PREADY and PSLVERR valid for the next PCLK rising edge, and PRDATA valid for when PREADY is driven high at the end of the "access" phase.
So simplicity of design is the answer to your first questions, and not sure what delay you are referrring to in your second.
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