the scenario is like :
for AXI4 FIXED burst type i am calculating lower_byte_lane and upper byte lanes for this control information
start_addr = 0001;
Number_bytes = 4;
burst_length = 4;
so now for the first transfer lower_byte_lane = 1 and upper_byte_lane = 3.
and for next transfers lower_byte_lane = 1 and upper_byte_lane = 4. why this lane value difference for FIXED burst type.AXI specification says that WSTRB value remains same for all transfers in FIXED burst.
For a FIXED burst type the "unaligned" start address applies for all transfers in the transaction (fixed means the address does not change). So it is byte lanes 1-3 that can be used for each of these transfers in this example.
The calculations shown on page A3-51 of the AXI protocol describing the byte lanes used for transfers are primarily for INCR bursts. WRAP bursts can use them but they are overly complex for WRAP burst types as you cannot have unaligned addresses in WRAP bursts. And for FIXED burst types the possible byte lanes used remain the same for each transfer, so only the "first transfer" calculation applies.
thanks for guidance
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