i am writing a verification code for handshaking. i want to assert the WVALIDin same ACLK cycle where the WVALIDis deasserted due to detecting the corresponding WREADY from the slave.
please give me some hint for this.
I'm not sure what you are asking for here as there isn't any question.
What your waveforms (both identical ?) show is simply a glitch following an ACLK rising edge when the master sees one data transfer end and it start the next. The control logic for WVALID is switching from a state waiting for WREADY to be sampled high to complete a handshake to the next state for a new transfer. WVALID is high in both these states in this sequence, but a glitch is possible when the driving state changes.
Is there something specific you are worried about ?
those waveform are of axi specifications. i just want to make high the WVALID in same ACLK cycle where the first transfer is complete.
If you are asking "can you assert WVALID for the next data transfer as soon as the master samples WREADY high from the slave on the ACLK rising edge (indicating the write data handshake completion)", yes, that is what these figures in the spec show.
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