Hi ARM experts,
I am configuring a network in which data width of busmatrix is 32bit and data with of slave is 64bit.
In write transaction, high half and low half of wstrb_slave[7:0] toggles interleavly, and it is quiet reasonable.
However, in read transaction, it seems that pl301 just bypasses the transaction from slave to master.
In my opinion, the duration of rvalid to master should be twice of the duration from slave.
How can I fix this problem?
I think for this sort of question you would need to email the ARM support addresses your company should have access to if it has license the PL301 directly from them. If you have not licensed this IP directly from ARM, please email whoever supplied you with the IP.
There are a number of factors that could affect how the PL301 might behave in this scenario, so when you do email the ARM support team (or whoever you got the IP from), please include a full set of waveforms (not just these selected signals) and also your PL301 configuration file.
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