While doing an unaligned transfer of 32-bit data on 64-bit data, using 0x001 address, lower address lines used to indicate an unaligned data transfer but what if this lower address line data also needs to be transferred? let say transfer size is 4.
The big question here is what is AWBURST signalling ?
If AWBURST indicates an INCR burst, the 4 transfers in your example would be to 0x001 (3 bytes) using WDATA[31:8], then 0x004 (4 bytes) on WDATA[63:32], 0x008 (4 bytes) on WDATA[31:0] and 0x00C (4 bytes) on WDATA[63:32]. So only the first transfer of the 4 is actually unaligned.
If AWBURST indicates a FIXED burst, the 4 transfers in your example would all be to 0x001 (3 bytes), each using WDATA[31:8]. Each transfer in a FIXED burst is to the same address, so all 4 would be unaligned.
If AWBURST indicates a WRAP burst, these do not allow unaligned start addresses.
Note that in the INCR and FIXED examples, where I have said 3 or 4 bytes in each data transfer that is the maximum number of bytes that could be transferred, and the WSTRB information for those transfers could signal fewer than the maximum.
how only 3 bytes are transferred in first transfer in INCR type burst, not whole 32-bits?
Because you used an unaligned start address.
The AXI protocol works best with aligned transfers, so by using an unaligned address you restrict the amount of data in an aligned range that you can transfer.
So using address 0x001 for a 32-bit INCR transfer tells the system that you will only be driving D[31:8] for the first transfer, and not D[7:0].
If you wanted to use the full 32-bits, use a 32-bit aligned start address.
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