Hi, AHB-newbie here.
For AHB-lite is there any way that the Slave may signal to the Master that it is not ready to accept any transactions?
Driving HREADY low only extends the data phase of the current transaction.
My understanding that the MASTER always expects the respective slave to always be ready to sample the Address on the Address Phase.
Is there also any way for the slave to tell the master that the current address phase needs to be extended?
Simple answer, no.
Sorry but the slave bus interface must always be able to accept a new transfer request (address phase), and only then once it is in the data phase of that request (if it is a NONSEQ or SEQ request) can it signal wait states to stall the master.
So even if internally your slave is busy with some other operation, the bus interface logic itself must be free to accept a request.
Thanks for the info.
Can I say that
1. Coming out of reset, all slaves must drive HREADY high
2. HREADY is only sampled by the MASTER on the data phase -- to check if wait states are needed.
For number 2, when HREADY has been detected low, can the Master continue to issue new transaction requests on the bus? Per my understanding, with HREADY low no slave will actually sample the HADDR
The coming out of reset case is a special one in that in theory there is no previous transfer address phase for the slaves to be responding to, but the requirement that the slaves all drive HREADY high just ensure that as soon as HRESETn is deasserted that any master state machine is free to move on to its first post-reset real address phase transfer, and then one further cycle later the first addressed slave can then respond to a real transfer data phase.
I suggest you to study the AHB wrapper RTL code, it would be helpful.
In fact, all AHB slave got both HREADY (input) and HREADYout port (output). And you can check with RTL code, the slave always sample the address and control signal but it will be active address phase when the HREADY is high.
In AHB-Lite, the bus will be occupied when the slave send WAIT request to the master. If your slave take a very long WAIT state, and you want to free the bus before the slave finish its work, maybe you should not make HREADYout to low, always make it Hi, and use the interrupt to inform the processor back to read the result of slave.
Just be careful for the data computing/processing dependence.
Another method is to build a multi-layer AHB bus.
Thanks for the recommendation.
I do know that driving HREADY low will occupy the bus until it is driven high again during normal operations.
My initial intention was to delay the bus operations coming out of reset. One of the slaves requires some startup time after reset release and I was wondering if pulling HREADY low coming out of reset will cause the address phase of the first transaction to be extended, but from what I gather it looks like it would not.
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