Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Pelion IoT Platform
Activity
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
More
Cancel
Developer Community
IP Products
System
Jump...
Cancel
System
SoC Design forum
AHB WRAP address boundaries
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
State
Not Answered
Replies
3 replies
Subscribers
71 subscribers
Views
11012 views
Users
0 members are here
AMBA
Bus Architecture
AHB
Related
AHB WRAP address boundaries
Offline
myarm myarm
over 6 years ago
Note: This was originally posted on 18th June 2008 at
http://forums.arm.com
AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should I re-calculate the wrap boundary based on hsize?
For example, I know from the spec that hsize = 2 and WRAP4 will sequence through addresses like this:
0x4 - 0x8 - 0xC - 0x0
Then, does hsize = 1 (halfword) and WRAP4, mean the sequence should be
0x4 - 0x6 - 0x8 - 0xA (using 4 word boundary)
or
0x4 - 0x6 - 0x0 - 0x2 (using 4 halfword boundary)?
Thanks!
Parents
0
Offline
myarm myarm
over 6 years ago
Note: This was originally posted on 18th June 2008 at
http://forums.arm.com
Thank you so much for your detailed explanation. It is now crystal clear to me.
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Reply
0
Offline
myarm myarm
over 6 years ago
Note: This was originally posted on 18th June 2008 at
http://forums.arm.com
Thank you so much for your detailed explanation. It is now crystal clear to me.
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Children
No data
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Not Answered
AXI4 transaction attributes
0
195
views
0
replies
Started
6 days ago
by
Ravi V.
Suggested Answer
AMBA 5 CHI Link Layer (L-Credit Return)
0
AMBA 5 CHI
CHI
Cache Coherent Interconnect
AMBA 5
1795
views
3
replies
Latest
7 days ago
by
Christopher Tory
Answered
Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?
0
AXI4
329
views
1
reply
Latest
8 days ago
by
Christopher Tory
Not Answered
BUSY transfer just before the last transfer in a burst by a AHB Master.
0
1324
views
1
reply
Latest
23 days ago
by
Colin Campbell
Not Answered
AMBA AXI reset
0
AMBA
AXI
7738
views
3
replies
Latest
23 days ago
by
Colin Campbell
>
View all questions in SoC Design forum