For AXI we are using AWSIZE(unaligned address = AWADDR % 2**AWSIZE). So for APB which size should we use to calculate unaligned address.
The APB protocol doesn't support unaligned transfers, so PADDR must be aligned to width of the data bus. On a 32-bit data bus implementation for example you would see PADDR step up 4 bytes at a time; 0x0, 0x4, 0x8...
When bridging to the APB protocol from other AMBA system buses (perhaps AHB or AXI) you will usually see the LSBs of PADDR are tied low, so meaningless unaligned accesses cannot then be signalled.
If you are using APB4 there is then the PSTRB signal to indicate which of the byte lanes of the data bus contain valid write data, but for read accesses (and write accesses for APB3 and earlier) the full width of the data bus is used for each APB transfer.