AMBA AXI reset

According to spec IHI0022D_amba_axi_protocol_spec  section A2.1 page number: A2-28

        "All signals are sampled on the rising edge of the global clock "

     Q) Should RESET_N also  be sampled on the rising edge only?

Section A3.1.2,  says

   "The AXI protocol uses a single active LOW reset signal, ARESETn. The reset signal can be asserted asynchronously, but de-assertion must be synchronous with a rising edge of ACLK.

During reset the following interface requirements apply:
• a master interface must drive ARVALID, AWVALID, and WVALID LOW

• a slave interface must drive RVALID and BVALID LOW


Q) How a design should implement with respect to reset. ( Should it implement Asynchronous reset)? 

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