JTAG for both SW Debug and HW Debug Test

Hi Experts,

I am currently architecting a mixed signal SoC containing a Cortex Mx core. We will have a single JTAG port that we want to use for both S/W debug and for H/W debug/test.  Examples of the H/W debug/test would be: Standard boundary scan (board test), plus internal test (INTEST, BIST, test mode selections/overrides etc)

I would therefore need two on-chip TAP controllers, and in principle I could simply chain them together (JTAG I/O -> H/W TAP -> ARM TAP -> JTAG I/O).  However, this would violate the JTAG standard, since when BYPASS was selected, the chain length would be 2 bits long instead of 1 (I think that there is a similar issue with the IDCODE instruction).

I assume that this is a problem that many people already solved, and was hoping that there was a recommended solution, or App note.

Thanks for any feedback.


More questions in this forum
There are no posts to show. This could be because there are no posts in this forum or due to a filter.