Debugging a Cortex-M0 Hard Fault

There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg

niallcooling's Developing a Generic Hard Fault handler for Armv7-M

also: - which references

But hard to find anything specifically for Cortex-M0 (or M0+)

The Armv6-M Architecture Reference Manual seems to be saying that many of the features that the above references rely upon are not provided in Cortex-M0; eg, there's no CFSR and no HFSR.

I have managed to implement a Hard Fault handler (from suggestions above), and it is called when a Hard Fault occurs - just not sure how much of the information is actually valid/useful once I'm there...



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